Bus Controller Operation In Reset; Usage Notes - Renesas H8SX/1650 Hardware Manual

Note, however, that the bus cannot be transferred in the following cases.
• During transfer information read
• During the first data transfer
• During transfer information write back
The DTC releases the bus when the consecutive transfer cycles completed.
(3)
External Bus Release
When the BREQ pin goes low and an external bus release request is issued while the BRLE bit in
BCR1 and the ICR bit of the corresponding pin are set to 1, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
6.15

Bus Controller Operation in Reset

In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
6.16

Usage Notes

(1)
Setting Registers
The BSC registers must be specified before accessing the external address space. When activating
the external ROM, specify the registers before external accesses other than the instruction fetch
from the external ROM are generated.
(2)
External Bus Release Function and All-Module-Clock-Stop Mode
In this LSI, if the ACSE bit in MSTPCRA is set to 1, and then a SLEEP instruction is executed
with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFFFFFF) or for
operation of the 8-bit timer module alone (MSTPCR = H'F[E to 0]FFFFFF), and a transition is
made to the sleep state, the all-module-clock-stop mode is entered in which the clock is also
stopped for the bus controller and I/O ports. For details, see section 18, Power-Down States.
In this state, the external bus release function is halted. To use the external bus release function in
sleep mode, the ACSE bit in MSTPCRA must be cleared to 0. Conversely, if a SLEEP instruction
to place the chip in all-module-clock-stop mode is executed in the external bus released state, the
transition to all-module-clock-stop mode is deferred and performed until after the bus is
recovered.
Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 215 of 666
REJ09B0311-0200