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Section 2 CPU
Figure 2.15 shows an example of specification of a branch address using this addressing mode.
Specified
by @aa:8
Figure 2.15 Branch Address Specification in Memory Indirect Mode
2.8.11
Extended Memory Indirect—@@vec:7
This mode is used in the JMP and JSR instructions. The operand value is a branch address, which
is the contents of a memory location pointed to by the following operation result: the sum of 7-bit
data in the instruction code and the value of H'80 is multiplied by 2 or 4.
The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to
H'0003FF in other modes. In assembler notation, an address to store a branch address is specified.
In normal mode, the memory location is pointed to by word-size data and the branch address is 16
bits long. In other modes, the memory location is pointed to by longword-size data. In middle or
advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).
2.8.12
Effective Address Calculation
Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. In
normal mode, the upper eight bits of the effective address are ignored in order to generate a 16-bit
address.
Rev.2.00 Jun. 28, 2007 Page 56 of 666
REJ09B0311-0200
Branch address
(a) Normal Mode
Reserved
Specified
by @aa:8
Branch address
(b) Advanced Mode
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