I/O Pins Used For Address/Data Multiplexed I/O Interface - Renesas H8SX/1650 Hardware Manual

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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6.9.4

I/O Pins Used for Address/Data Multiplexed I/O Interface

Table 6.19 shows the pins used for the address/data multiplexed I/O Interface.
Table 6.19 I/O Pins for Address/Data Multiplexed I/O Interface
When Byte
Control
SRAM is
Pin
Specified
CSn
CSn
AS/AH
AH*
RD
RD
LHWR/LUB
LHWR
LLWR/LLB
LLWR
D15 to D0
D15 to D0
A23 to A0
A23 to A0
WAIT
WAIT
BS
BS
RD/WR
RD/WR
The AH output is multiplexed with the AS output. At the timing that an area is specified
Note:
*
as address/data multiplexed I/O, this pin starts to function as the AH output meaning
that this pin cannot be used as the AS output. At this time, when other areas set to the
basic bus interface is accessed, this pin does not function as the AS output. Until an
area is specified as address/data multiplexed I/O, be aware that this pin functions as
the AS output.
Name
I/O
Chip select
Output
Address hold
Output
Read strobe
Output
Low-high write Output
Low-low write Output
Address/data
Input/
output
Address
Output
Wait
Input
Bus cycle start Output
Read/write
Output
Section 6 Bus Controller (BSC)
Function
Chip select (n = 3 to 7) when area n is specified as the
address/data multiplexed I/O space
Signal to hold an address when the address/data
multiplexed I/O space is specified
Signal indicating that the address/data multiplexed I/O
space is being read
Strobe signal indicating that the upper bytes (D15 to
D8) is valid when the address/data multiplexed I/O
space is written
Strobe signal indicating that the lower bytes (D7 to D0)
is valid when the address/data multiplexed I/O space
is written
Address and data multiplexed pins for the
address/data multiplexed I/O space.
Only D7 to D0 are valid when the 8-bit space is
specified. D15 to D0 are valid when the 16-bit space is
specified.
Address output pin
Wait request signal used when the external address
space is accessed
Signal to indicate the bus cycle start
Signal indicating the data bus input or output direction
Rev.2.00 Jun. 28, 2007 Page 191 of 666
REJ09B0311-0200

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