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Item
SCI
Transmit data delay time
Receive data setup time
(clocked synchronous)
Receive data hold time
(clocked synchronous)
A/D
Trigger input setup time
converter
Pφ
Output compare
output*
Input capture
input*
Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Pφ
TCLKA to TCLKD
Symbol
t
TXD
t
RXS
t
RXH
t
TRGS
Pφ
Ports 1 to 3, 5, 6, A,
B, D to F, H, I (read)
Ports 1 to 3, 6, A,
B, D to F, H, I (write)
Figure 20.21 I/O Port Input/Output Timing
t
TOCD
Figure 20.22 TPU Input/Output Timing
t
TCKWL
Figure 20.23 TPU Clock Input Timing
Section 20 Electrical Characteristics
Min.
Max.
40
40
40
30
T
T
1
2
t
t
PRS
PRH
t
PWD
t
TICS
t
TCKS
t
TCKWH
Rev.2.00 Jun. 28, 2007 Page 641 of 666
Unit
Test Conditions
ns
Figure 20.30
ns
ns
ns
Figure 20.31
t
TCKS
REJ09B0311-0200
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