Chip Select Signals - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.5.3

Chip Select Signals

This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external address space area is accessed. Figure 6.8 shows an example of CSn (n
= 0 to 7) signal output timing.
Enabling or disabling of CSn signal output is set by the port function control register (PFCR). For
details, see section 8.3, Port Function Controller.
In on-chip ROM disabled extended mode, pin CS0 is placed in the output state after a reset. Pins
CS1 to CS7 are placed in the input state after a reset and so the corresponding PFCR bits should
be set to 1 when outputting signals CS1 to CS7.
In on-chip ROM enabled extended mode, pins CS0 to CS7 are all placed in the input state after a
reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS0 to CS7.
The PFCR can specify multiple CS outputs for a pin. If multiple CSn outputs are specified for a
single pin by the PFCR, CS to be output are generated by mixing all the CS signals. In this case,
the settings for the external bus interface areas in which the CSn signals are output to a single pin
should be the same.
Figure 6.9 shows the signal output timing when the CS signals to be output to areas 5 and 6 are
output to the same pin.
Bφ
Address bus
CSn
Rev.2.00 Jun. 28, 2007 Page 154 of 666
REJ09B0311-0200
T
1
Figure 6.8 CSn Signal Output Timing (n = 0 to 7)
Bus cycle
T
2
External address of area n
T
3