Operation In Asynchronous Mode - Renesas H8SX/1650 Hardware Manual

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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13.4

Operation in Asynchronous Mode

Figure 13.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high
level). In asynchronous serial communication, the communication line is usually held in the mark
state (high level). The SCI monitors the communication line, and when it goes to the space state
(low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter
and receiver are independent units, enabling full-duplex communication. Both the transmitter and
the receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transmission and reception.
1
Serial
data
Figure 13.2 Data Format in Asynchronous Communication
LSB
0
D0
D1
D2
D3
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
One unit of transfer data (character or frame)
(Example with 8-Bit Data, Parity, Two Stop Bits)
Section 13 Serial Communication Interface (SCI)
MSB
D4
D5
D6
D7
0/1
Parity
bit
1 bit or
none
Rev.2.00 Jun. 28, 2007 Page 481 of 666
Idle state
(mark state)
1
1
1
Stop bit
1 or 2
bits
REJ09B0311-0200

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