Renesas H8SX/1650 Hardware Manual page 487

Bit Bit Name
4 FER
3 PER
Initial
Value R/W Description
0 R/(W)* Framing Error
Indicates that a framing error has occurred during
reception in asynchronous mode and the reception
ends abnormally.
[Setting condition]
•
[Clearing condition]
•
0 R/(W)* Parity Error
Indicates that a parity error has occurred during
reception in asynchronous mode and the reception
ends abnormally.
[Setting condition]
•
[Clearing condition]
•
Section 13 Serial Communication Interface (SCI)
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is checked
whether it is 1 but the second stop bit is not
checked. Note that receive data when the framing
error occurs is transferred to RDR, however, the
RDRF flag is not set. In addition, when the FER flag
is being set to 1, the subsequent serial reception
cannot be performed. In clocked synchronous
mode, serial transmission also cannot continue.
When 0 is written to FER after reading FER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the FER
flag is not affected and retains its previous value.
When a parity error is detected during reception
Receive data when the parity error occurs is
transferred to RDR, however, the RDRF flag is not
set. Note that when the PER flag is being set to 1,
the subsequent serial reception cannot be
performed. In clocked synchronous mode, serial
transmission also cannot continue.
When 0 is written to PER after reading PER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the PER
bit is not affected and retains its previous value.
Rev.2.00 Jun. 28, 2007 Page 465 of 666
REJ09B0311-0200