Usage Notes; Module Stop State Setting; Input Clock Restrictions - Renesas H8SX/1650 Hardware Manual

9.9

Usage Notes

9.9.1

Module Stop State Setting

Operation of the TPU can be disabled or enabled using the module stop control register. The initial
setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop
state. For details, see section 18, Power-Down States.
9.9.2

Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.45 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Note: Phase difference, Overlap
Pulse width
Figure 9.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Phase Phase
difference difference
Overlap Overlap
Pulse width
1.5 states
2.5 states
Section 9 16-Bit Timer Pulse Unit (TPU)
Pulse width
Pulse width
Rev.2.00 Jun. 28, 2007 Page 381 of 666
Pulse width
REJ09B0311-0200