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(2)
16-Bit 3-State Access Space
Figures 6.17 to 6.19 show the bus timing of 16-bit 3-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be
inserted.
Read
Write
Notes: 1. n = 0 to 7
Bφ
Address
CSn
AS
RD
D15 to D8
D7 to D0
LHWR
LLWR
D15 to D8
D7 to D0
BS
RD/WR
2. When RDNn = 0
Figure 6.17 16-Bit 3-State Access Space Bus Timing
(Byte Access for Even Address)
Bus cycle
T
T
1
2
High level
Valid
High-Z
Rev.2.00 Jun. 28, 2007 Page 171 of 666
Section 6 Bus Controller (BSC)
T
3
Valid
Invalid
REJ09B0311-0200
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