Renesas H8SX/1650 Hardware Manual page 490

Section 13 Serial Communication Interface (SCI)
Bit Bit Name
4 ERS
3 PER
Rev.2.00 Jun. 28, 2007 Page 468 of 666
REJ09B0311-0200
Initial
Value R/W Description
0 R/(W)* Error Signal Status
[Setting condition]
•
[Clearing condition]
•
0 R/(W)* Parity Error
Indicates that a parity error has occurred during
reception in asynchronous mode and the reception
ends abnormally.
[Setting condition]
•
[Clearing condition]
•
When a low error signal is sampled
When 0 is written to ERS after reading ERS = 1
When a parity error is detected during reception
Receive data when the parity error occurs is
transferred to RDR, however, the RDRF flag is not
set. Note that when the PER flag is being set to 1,
the subsequent serial reception cannot be
performed. In clocked synchronous mode, serial
transmission also cannot continue.
When 0 is written to PER after reading PER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the PER
flag is not affected and retains its previous value.