Renesas H8SX/1650 Hardware Manual page 446

Section 11 8-Bit Timers (TMR)
Bit Bit Name
6 CMFA
5 OVF

4
3 OS3
2 OS2
1 OS1
0 OS0
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.
2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first
compare match occurs after resetting.
Rev.2.00 Jun. 28, 2007 Page 424 of 666
REJ09B0311-0200
Initial
Value R/W Description
1
0 R/(W)* Compare Match Flag A
[Setting condition]
When TCNT matches TCORA
[Clearing conditions]
•
•
1
0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0
to OVF
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
1 R Reserved
This is a read-only bit and cannot be modified.
0 R/W Output Select 3 and 2*
0 R/W These bits select a method of TMO pin output when
compare match B of TCORB and TCNT occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B occurs
0 R/W Output Select 1 and 0*
0 R/W These bits select a method of TMO pin output when
compare match A of TCORA and TCNT occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A occurs
When writing 0 after reading CMFA = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When the DTC is activated by a CMIA interrupt
while the DISEL bit in MRB of the DTC is 0
2
(toggle output)
2
(toggle output)