Renesas H8SX/1650 Hardware Manual page 173

Name
Low-low write/lower-lower byte
select
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Chip select 5
Chip select 6
Chip select 7
Wait
Bus request
Bus request acknowledge
Bus request output
External bus clock
Symbol I/O
LLWR/LLB Output
CS0
Output
CS1
Output
CS2
Output
CS3
Output
CS4
Output
CS5
Output
CS6
Output
CS7
Output
WAIT
Input
BREQ
Input
BACK
Output
BREQO
Output
Bφ Output
Section 6 Bus Controller (BSC)
Function
•
Strobe signal indicating that the basic
bus, burst ROM, or address/data
multiplexed I/O space is written to, and
the lower byte (D7 to D0) of data bus is
enabled
•
Strobe signal indicating that the byte
control SRAM space is accessed, and
the lower byte (D7 to D0) of data bus is
enabled
Strobe signal indicating that area 0 is
selected
Strobe signal indicating that area 1 is
selected
Strobe signal indicating that area 2 is
selected
Strobe signal indicating that area 3 is
selected
Strobe signal indicating that area 4 is
selected
Strobe signal indicating that area 5 is
selected
Strobe signal indicating that area 6 is
selected
Strobe signal indicating that area 7 is
selected
Wait request signal when accessing
external address space.
Request signal for release of bus to
external bus master
Acknowledge signal indicating that bus has
been released to external bus master
External bus request signal used when
internal bus master accesses external
address space in the external-bus released
state
External bus clock
Rev.2.00 Jun. 28, 2007 Page 151 of 666
REJ09B0311-0200