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14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 14.4 shows the A/D conversion timing. Table 14.3 indicates
the A/D conversion time.
As indicated in figure 14.4, the A/D conversion time (t
(t
). The length of t
SPL
D
conversion time therefore varies within the ranges indicated in table 14.3.
In scan mode, the values given in table 14.3 apply to the first conversion time. The values given in
table 14.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in
ADCR should be set so that the conversion time is within the ranges indicated by the A/D
conversion characteristics.
Address
Write signal
Input sampling
timing
ADF
varies depending on the timing of the write access to ADCSR. The total
(1)
Pφ
(2)
t
D
[Legend]
(1):
ADCSR write cycle
(2):
ADCSR address
t
A/D conversion start delay time
D:
t
:
Input sampling time
SPL
t
: A/D conversion time
CONV
Figure 14.4 A/D Conversion Timing
) passes after the ADST bit in ADCSR is set to
D
) includes t
CONV
t
SPL
t
CONV
Rev.2.00 Jun. 28, 2007 Page 535 of 666
Section 14 A/D Converter
and the input sampling time
D
REJ09B0311-0200
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