Block Diagram - Renesas H8SX/1650 Hardware Manual

Section 1 Overview
1.3

Block Diagram

RAM
H8SX
CPU
DTC
Clock pulse
generator
[Legend]
CPU:
Central processing unit
DTC:
Data transfer controller
BSC:
Bus controller
WDT:
Watchdog timer
Rev.2.00 Jun. 28, 2007 Page 8 of 666
REJ09B0311-0200
Interrupt
controller
BSC
TMR:
8-bit timer
TPU:
16-bit timer pulse unit
PPG:
Programmable pulse generator
SCI:
Serial communications interface
Figure 1.2 Block Diagram
WDT
TMR (unit 0)
× 2 channels
TMR (unit 1)
× 2 channels
TPU × 6 channels
PPG
SCI × 4 channels
A/D converter
D/A converter
Port 1
Port 2
Port 3
Port 5
Port 6
Port A
Port B
Port D
Port E
Port F
Port H
Port I