Renesas H8SX/1650 Hardware Manual page 35

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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Classification
Pin Name
16-bit timer
TIOCA2
pulse unit (TPU)
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Programmable
PO15 to PO0
pulse generator
(PPG)
8-bit timer
TMO0 to TMO3
(TMR)
TMCI0 to TMCI3
TMRI0 to TMRI3
WDTOVF
Watchdog timer
(WDT)
Serial
TxD0 to TxD4
communication
interface (SCI)
RxD0 to RxD4
SCK0 to SCK4
I/O
Description
Input/
Signals for TGRA_2 and TGRB_2. These pins are used as
output
input capture inputs, output compare outputs, or PWM
outputs.
Input/
Signals for TGRA_3 to TGRD_3. These pins are used as
output
input capture inputs, output compare outputs, or PWM
outputs.
Input/
Signals for TGRA_4 and TGRB_4. These pins are used as
output
input capture inputs, output compare outputs, or PWM
outputs.
Input/
Signals for TGRA_5 and TGRB_5. These pins are used as
output
input capture inputs, output compare outputs, or PWM
outputs.
Output
Output pins for the pulse signals.
Output
Output pins for the compare match signals.
Input
Input pins for the external clock signals that drive for the
counters.
Input
Input pins for the counter-reset signals.
Output
Output pin for the counter-overflow signal in watchdog-timer
mode.
Output
Output pins for data transmission.
Input
Input pins for data reception.
Input/
Input/output pins for clock signals.
output
Section 1 Overview
Rev.2.00 Jun. 28, 2007 Page 13 of 666
REJ09B0311-0200

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