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2.8.8
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,
which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of
the PC contents. The 8-bit or 16-bit displacement is sign-extended when added to the PC contents.
The PC contents to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or −32766
to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting value
should be an even number. In advanced mode, only the lower 24 bits of this branch address are
valid; the upper eight bits are all assumed to be 0 (H'00).
2.8.9
Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC), or
@(ERn.L, PC)
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,
which is the sum of the following operation result and the 32-bit address of the PC contents:
specified bits of the contents of an address register (RnL, Rn, or ERn) specified by the register
field in the instruction code is zero-extended to 32-bit data and multiplied by 2.
The PC content to which the displacement is added is the address of the first byte of the next
instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper
eight bits are all assumed to be 0 (H'00).
2.8.10
Memory Indirect—@@aa:8
This mode is used in the JMP and JSR instructions. The operand value is a branch address, which
is the content of a memory location pointed to by an 8-bit absolute address in the instruction code.
The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range to store a
branch address is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other
modes). In normal mode, the memory location is pointed to by word-size data and the branch
address is 16 bits long. In other modes, the memory location is pointed to by longword-size data.
In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).
Note that the top part of the address range is also used as the exception handling vector area. A
vector address of an exception handling other than a reset or a CPU address error can be changed
by VBR.
Rev.2.00 Jun. 28, 2007 Page 55 of 666
REJ09B0311-0200
Section 2 CPU
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