Table of Contents
Advertisement
Section 5 Interrupt Controller
5.7
CPU Priority Control Function Over DTC
The interrupt controller has a function to control the priority between the DTC and the CPU by
assigning a priority levels to the DTC and CPU. Since the priority level can automatically be
assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt
exception handling prior to the DTC transfer.
The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level
of the DTC is assigned by bits DTCP2 to DTCP0 in CPUPCR.
The priority control function over the DTC is enabled by setting the CPUPCE bit in CPUPCR to
1. When the CPUPCE bit is 1, the DTC activation source is controlled according to the respective
priority level.
The DTC activation source is controlled according to the priority level of the CPU indicated by
bits CPUP2 to CPUP0 and the priority level of the DTC indicated by bits DTCP2 to DTCP0. If the
CPU has priority, the DTC activation source is held. The DTC is activated when the condition by
which the activation source is held is cancelled (CPUCPCE = 1 and value of bits CPUP2 to
CPUP0 is greater than that of bits DTCP2 to DTCP0). The priority level of the DTC is assigned by
the DTCP2 to DTCP0 bits in CPUPCR regardless of the activation source.
There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR.
Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt
mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function
to automatically assign the priority level. Therefore, the priority level is assigned directly by
software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the
CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0
bits in EXR).
The priority level which is automatically assigned when the IPSETE bit is 1 differs according to
the interrupt control mode.
In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1
and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU
are reflected in bits CPUP2 to CPUP0.
Rev.2.00 Jun. 28, 2007 Page 115 of 666
REJ09B0311-0200
Advertisement
Table of Contents
