Table of Contents
Advertisement
17.5
Usage Notes
17.5.1
Notes on Clock Pulse Generator
1. The following points should be noted since the frequency of φ (Iφ: system clock, Pφ:
peripheral module clock, Bφ: external bus clock) supplied to each module changes according
to the setting of SCKCR.
Select a clock division ratio that is within the operation guaranteed range of clock cycle time
t
shown in the AC timing of electrical characteristics.
cyc
For example, the following settings are not permitted under the conditions of 8 MHz ≤ Iφ ≤ 50
MHz, 8 MHz ≤ Pφ ≤ 35 MHz, and 8 MHz ≤ Bφ ≤ 50 MHz: Iφ < 8 MHz, 50 MHz < Iφ, Pφ < 8
MHz, 35 MHz < Pφ, Bφ < 8 MHz, and 50 MHz < Bφ.
2. All the on-chip peripheral modules (except for the DTC) operate on the Pφ. Therefore, note
that the time processing of modules such as a timer and SCI differs before and after changing
the clock division ratio.
In addition, wait time for clearing software standby mode differs by changing the clock
division ratio. For details, see section 18.7.3, Setting Oscillation Settling Time after Clearing
Software Standby Mode.
3. The relationship among the system clock, peripheral module clock, and external bus clock is Iφ
≥ Pφ and Iφ ≥ Bφ. In addition, the system clock setting has the highest priority. Accordingly,
Pφ or Bφ may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits
PCK2 to PCK0 or BCK2 to BCK0.
4. Figure 17.5 shows the clock modification timing. After a value is written to SCKCR, this LSI
waits for the current bus cycle to complete. After the current bus cycle completes, each clock
frequency will be modified within one cycle (worst case) of the external input clock.
Section 17 Clock Pulse Generator
Rev.2.00 Jun. 28, 2007 Page 559 of 666
REJ09B0311-0200
Advertisement
Table of Contents
