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Figure 6.33 shows an example of the operation. In the figure, both bus cycles A and B are read
access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown
in (a), and an example of avoiding the data conflict by the CS assertion period extension cycle in
(b).
Bφ
Address bus
CS
AH
RD
Data bus
Bφ
Address bus
CS
AH
RD
Data bus
Figure 6.33 Consecutive Read Accesses to Same Area
Bus cycle A
Data hold time is long.
(a) Without CS assertion period extension cycle (CSXTn = 0)
Bus cycle A
(b) With CS assertion period extension cycle (CSXTn = 1)
(Address/Data Multiplexed I/O Space)
Section 6 Bus Controller (BSC)
Bus cycle B
Data conflict
Bus cycle B
Rev.2.00 Jun. 28, 2007 Page 197 of 666
REJ09B0311-0200
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