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Bφ
WAIT
Address
CSn
AS
RD
Read
Data bus
LHWR, LLWR
Write
Data bus
BS
RD/WR
Notes: 1. Upward arrows indicate the timing of WAIT pin sampling.
2. n = 0 to 7
3. RDNn = 0
Figure 6.20 Example of Wait Cycle Insertion Timing
Wait by
program
wait
T
T
T
1
1
pw
Write data
Section 6 Bus Controller (BSC)
Wait by WAIT pin
T
T
tw
tw
Rev.2.00 Jun. 28, 2007 Page 175 of 666
T
3
Read
data
REJ09B0311-0200
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