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Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.26 TIORL_3
Bit 3
Bit 2
Bit 1
IOC3
IOC2
IOC1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
1
X
[Legend]
X:
Don't care
Note:
*
When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.2.00 Jun. 28, 2007 Page 334 of 666
REJ09B0311-0200
Bit 0
TGRC_3
IOC0
Function
0
Output
compare
1
register*
0
1
0
1
0
1
0
Input
capture
register*
1
X
X
Description
TIOCC3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCC3 pin
Input capture at rising edge
Capture input source is TIOCC3 pin
Input capture at falling edge
Capture input source is TIOCC3 pin
Input capture at both edges
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
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