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6.8.5
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion by the WAIT
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.6.4,
Wait Control. Wait cycles cannot be inserted in a burst cycle.
6.8.6
Read Strobe (RD) Timing
When the burst ROM space is read by the CPU, the RDNCR setting for the corresponding space is
invalid.
The read strobe negation timing is the same timing as when RDNn = 0 in the basic bus interface.
6.8.7
Extension of Chip Select (CS) Assertion Period
In the burst ROM interface, the extension cycles can be inserted in the same way as the basic bus
interface.
For the burst ROM space, the burst access can be enabled only in read access by the CPU. In this
case, the setting of the corresponding CSXTn bit in CSACR is ignored and an extension cycle can
be inserted only before the full access cycle. Note that no extension cycle can be inserted before or
after the burst access cycles.
In read accesses by the CPU, the burst ROM space is equivalent to the basic bus interface space.
Accordingly, extension cycles can be inserted before and after the burst access cycles.
6.9
Address/Data Multiplexed I/O Interface
If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this
LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed
I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly
to this LSI.
6.9.1
Address/Data Multiplexed I/O Space Setting
Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be
specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in
MPXCR.
Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 189 of 666
REJ09B0311-0200
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