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Module stop mode .................................. 583
Multi-clock mode ................................... 573
Multiprocessor bit................................... 492
Multiprocessor communication
function................................................... 492
N
NMI interrupt.......................................... 100
Nonlinearity error ................................... 538
Non-overlapping..................................... 404
Normal transfer mode ............................. 236
O
Offset error ............................................. 538
On-chip baud rate generator ................... 484
On-chip ROM disabled extended mode.... 61
Open-drain control register..................... 262
Oscillator ................................................ 557
Output buffer control .............................. 262
Output trigger ......................................... 404
Overflow......................................... 429, 442
P
Package dimensions................................ 651
Parity bit ................................................. 481
Peripheral module clock (Pφ) ......... 146, 553
Pin assignments .......................................... 9
Pin functions ............................................. 10
PLL circuit...................................... 553, 558
Port function controller........................... 292
Port register............................................. 259
Power-down states .................................. 563
Processing states ....................................... 59
Product lineup......................................... 650
Program execution state............................ 59
Program stop state .................................... 59
Programmable pulse generator (PPG) .... 389
Pull-up MOS control register.................. 261
Q
Quantization error ................................... 538
R
RAM ....................................................... 551
Read strobe (RD) timing ......................... 176
Register addresses................................... 588
Register bits ............................................ 597
Register configuration in each port ......... 257
Registers
ABWCR...................... 124, 590, 599, 609
ADCR ......................... 531, 594, 604, 613
ADCSR ....................... 529, 594, 604, 613
ADDR ......................... 528, 594, 603, 613
ASTCR........................ 126, 590, 599, 609
BCR1 .......................... 137, 590, 599, 609
BCR2 .......................... 139, 590, 599, 609
BROMCR ................... 142, 590, 599, 609
BRR ............................ 471, 594, 603, 612
CCR ...................................................... 26
CPUPCR ....................... 89, 592, 602, 611
CRA .................................................... 224
CRB .................................................... 224
CSACR ....................... 133, 590, 599, 609
DACR01 ..................... 547, 593, 603, 612
DADR0 ....................... 546, 593, 603, 612
DADR1 ....................... 546, 593, 603, 612
DAR.................................................... 223
DDR............................ 258, 588, 597, 607
DR............................... 259, 588, 597, 607
DTCCR ....................... 226, 592, 602, 611
DTCER ....................... 225, 592, 601, 611
DTCVBR .................... 227, 590, 599, 609
ENDIANCR................ 140, 590, 599, 609
EXR ...................................................... 28
ICR.............................. 260, 588, 597, 607
Rev.2.00 Jun. 28, 2007 Page 663 of 666
REJ09B0311-0200
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