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Section 18 Power-Down States
18.5
Sleep Mode
18.5.1
Transition to Sleep Mode
When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep
mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are
retained. Other peripheral functions do not stop.
18.5.2
Clearing Sleep Mode
Sleep mode is exited by any interrupt, signals on the RES or STBY pin, and a reset caused by a
watchdog timer overflow.
1. Clearing by interrupt
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
2. Clearing by RES pin
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high makes the CPU start the reset exception processing.
3. Clearing by STBY pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
4. Clearing by reset caused by watchdog timer overflow
Sleep mode is exited by an internal reset caused by a watchdog timer overflow.
Rev.2.00 Jun. 28, 2007 Page 574 of 666
REJ09B0311-0200
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