Renesas H8SX/1650 Hardware Manual page 18

11.6.2 Compare Match Count Mode............................................................................ 430
11.7 Interrupt Sources............................................................................................................... 431
11.7.1 Interrupt Sources and DTC Activation ............................................................. 431
11.7.2 A/D Converter Activation................................................................................. 431
11.8 Usage Notes ...................................................................................................................... 432
11.8.1 Notes on Setting Cycle ..................................................................................... 432
11.8.2 Conflict between TCNT Write and Clear ......................................................... 432
11.8.3 Conflict between TCNT Write and Increment.................................................. 433
11.8.4 Conflict between TCOR Write and Compare Match........................................ 433
11.8.5 Conflict between Compare Matches A and B................................................... 434
11.8.6 Switching of Internal Clocks and TCNT Operation ......................................... 434
11.8.7 Mode Setting with Cascaded Connection ......................................................... 436
11.8.8 Module Stop State Setting ................................................................................ 436
11.8.9 Interrupts in Module Stop State ........................................................................ 436
Section 12 Watchdog Timer (WDT) ................................................................. 437
12.1 Features............................................................................................................................. 437
12.2 Input/Output Pin ............................................................................................................... 438
12.3 Register Descriptions........................................................................................................ 438
12.3.1 Timer Counter (TCNT)..................................................................................... 438
12.3.2 Timer Control/Status Register (TCSR)............................................................. 439
12.3.3 Reset Control/Status Register (RSTCSR)......................................................... 441
12.4 Operation .......................................................................................................................... 442
12.4.1 Watchdog Timer Mode..................................................................................... 442
12.4.2 Interval Timer Mode......................................................................................... 444
12.5 Interrupt Source ................................................................................................................ 444
12.6 Usage Notes ...................................................................................................................... 445
12.6.1 Notes on Register Access ................................................................................. 445
12.6.2 Conflict between Timer Counter (TCNT) Write and Increment....................... 446
12.6.3 Changing Values of Bits CKS2 to CKS0.......................................................... 446
12.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode............. 446
12.6.5 Internal Reset in Watchdog Timer Mode.......................................................... 447
System Reset by WDTOVF Signal................................................................... 447
12.6.6
12.6.7 Transition to Watchdog Timer Mode or Software Standby Mode.................... 447
Section 13 Serial Communication Interface (SCI)............................................ 449
13.1 Features............................................................................................................................. 449
13.2 Input/Output Pins.............................................................................................................. 451
13.3 Register Descriptions........................................................................................................ 452
13.3.1 Receive Shift Register (RSR) ........................................................................... 454
Rev.2.00 Jun. 28, 2007 Page xviii of xxii