Renesas H8SX/1650 Hardware Manual page 187

(2)
16-Bit Access Space
With the 16-bit access space, the upper byte data bus (D15 to D8) and lower byte data bus (D7 to
D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one
word.
Figures 6.12 and 6.13 illustrate data alignment control for the 16-bit access space. Figure 6.12
shows the data alignment when the data endian format is specified as big endian. Figure 6.13
shows the data alignment when the data endian format is specified as little endian.
In big endian, byte access for an even address is performed by using the upper byte data bus and
byte access for an odd address is performed by using the lower byte data bus.
In little endian, byte access for an even address is performed by using the lower byte data bus, and
byte access for an odd address is performed by using the upper byte data bus.
Access
Access
Size
Address
Even
Byte
(2n)
Odd
(2n+1)
Even
Word
(2n)
Odd
(2n+1)
Longword Even
(2n)
Odd
(2n+1)
Figure 6.12 Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian)
Access
Bus
Count
Cycle Data Size
1st
Byte
1
1st
1 Byte
1
1st Word
2
Byte
1st
2nd Byte
2 Word
1st
Word
2nd
1st
Byte
3
2nd Word
3rd
Byte
Section 6 Bus Controller (BSC)
Strobe signal
LHWR/LUB
D15
7
15
7
31
15
23
7
Rev.2.00 Jun. 28, 2007 Page 165 of 666
REJ09B0311-0200
LLWR/LLB
RD
Data bus
D8 D7 D0
0
7
0
7
8 0
15
8
0
16
24 23
8
7 0
31 24
16 15 8
0