Renesas H8SX/1650 Hardware Manual page 66

Section 2 CPU
Table 2.8 Shift Operation Instructions
Instruction Size
SHLL B/W/L
SHLR
SHAL B/W/L
SHAR
ROTL B/W/L
ROTR
ROTXL B/W/L
ROTXR
Table 2.9 Bit Manipulation Instructions
Instruction Size
BSET B
BSET/cc B
BCLR B
Rev.2.00 Jun. 28, 2007 Page 44 of 666
REJ09B0311-0200
Function
(EAd) (shift) → (EAd)
Performs a logical shift on the contents of a general register or a memory
location.
The contents of a general register or a memory location can be shifted by
1, 2, 4, 8, or 16 bits. The contents of a general register can also be shifted
by any bits. In this case, the number of bits is specified by 5-bit immediate
data or the lower 5 bits of general register contents.
(EAd) (shift) → (EAd)
Performs an arithmetic shift on the contents of a general register or a
memory location.
1-bit or 2-bit shift is possible.
(EAd) (rotate) → (EAd)
Rotates the contents of a general register or a memory location.
1-bit or 2-bit rotation is possible.
(EAd) (rotate) → (EAd)
Rotates the contents of a general register or a memory location with the
carry flag.
1-bit or 2-bit rotation is possible.
Function
1 → (<bit-No.> of <EAd>)
Sets a specified bit in the contents of a general register or a memory
location to 1. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
if cc, 1 → (<bit-No.> of <EAd>)
If the specified condition is satisfied, this instruction sets a specified bit in
a memory location to 1. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.
0 → (<bit-No.> of <EAd>)
Clears a specified bit in the contents of a general register or a memory
location to 0. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.