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Section 4 Exception Handling
Bφ
RES
Address bus
RD
HWR, LWR
D15 to D0
(1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2)(4))
(6) First instruction in the exception handling routine
Note: * Seven program wait cycles are inserted.
(16-Bit External Access in On-chip ROM Disabled Advanced Mode)
Rev.2.00 Jun. 28, 2007 Page 74 of 666
REJ09B0311-0200
Vector fetch
*
(1)
(2)
Figure 4.2 Reset Sequence
Internal
First instruction
operation
prefetch
*
*
(3)
(5)
High
(4)
(6)
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