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Section 9 16-Bit Timer Pulse Unit (TPU)
TCNT value
TGRA
TGRB
H'0000
TIOCA
Figure 9.22 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as
the duty cycle.
TCNT value
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Rev.2.00 Jun. 28, 2007 Page 362 of 666
REJ09B0311-0200
Figure 9.21 Example of PWM Mode Operation (1)
Figure 9.22 Example of PWM Mode Operation (2)
Counter cleared by
TGRA compare match
Counter cleared by
TGRB_1 compare match
Time
Time
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