Renesas H8SX/1650 Hardware Manual page 156

Section 6 Bus Controller (BSC)
Bit Bit Name
15 CSXH7
14 CSXH6
13 CSXH5
12 CSXH4
11 CSXH3
10 CSXH2
9 CSXH1
8 CSXH0
7 CSXT7
6 CSXT6
5 CSXT5
4 CSXT4
3 CSXT3
2 CSXT2
1 CSXT1
0 CSXT0
Note: In burst ROM interface, the CSXTn settings are ignored.
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Rev.2.00 Jun. 28, 2007 Page 134 of 666
REJ09B0311-0200
Initial
Value R/W Description
CS and Address Signal Assertion Period Control 1
0 R/W
0 R/W These bits specify whether or not the Th cycle is to be
inserted (see figure 6.3). When an area for which bit
0 R/W
CSXHn is set to 1 is accessed, one Th cycle, in which the
0 R/W CSn and address signals are asserted, is inserted before
the normal access cycle.
0 R/W
0: In access to area n, the CSn and address assertion
0 R/W
0 R/W
1: In access to area n, the CSn and address assertion
0 R/W
(n = 7 to 0)
CS and Address Signal Assertion Period Control 2
0 R/W
0 R/W These bits specify whether or not the Tt cycle is to be
inserted (see figure 6.3). When an area for which bit
0 R/W
CSXTn is set to 1 is accessed, one Tt cycle, in which the
CSn and address signals are retained, is inserted after
0 R/W
the normal access cycle.
0 R/W
0: In access to area n, the CSn and address assertion
0 R/W
0 R/W
1: In access to area n, the CSn and address assertion
0 R/W
(n = 7 to 0)
period (Th) is not extended
period (Th) is extended
period (Tt) is not extended
period (Tt) is extended