Renesas H8SX/1650 Hardware Manual page 681

Item
8.3.2 Port Function Control
Register 1 (PFCR1)
17.5.1 Notes on Clock Pulse
Generator
19.2 Register Bits
Page Revision (See Manual for Details)
293, Modified
294
Bit Bit Name
7 CS7SA*
6 CS7SB*
5 CS6SA*
4 CS6SB*
3 CS5SA*
2 CS5SB*
1 CS4SA*
0 CS4SB*
Note: * If multiple CS outputs are specified to a single
pin according to the CSn output pin select bits
(n = 4 to 7), ...
559 Deleted
4. Note that the frequency of f will be changed in the
middle of a bus cycle when setting SCKCR while
executing the external bus cycle with the write-data-
buffer function.
598 Modified
Register
Abbreviation
PFCR1
Main Revisions and Additions in this Edition
0
2 1
CS5SB CS4SA CS4SB
0 0 0
R/W R/W R/W
Description
CS7 Output Pin Select
:
10: Specifies pin PF7 as CS7-C output
11: Setting prohibited
CS6 Output Pin Select
:
10: Specifies pin PF7 as CS6-C output
11: Specifies pin PF6 as CS6-D output
CS5 Output Pin Select
:
10: Specifies pin PF7 as CS5-C output
11: Specifies pin PF5 as CS5-D output
CS4 Output Pin Select
Selects the output pin for CS4 when CS4
output is enabled (CS4E = 1)
00: Specifies pin PB0 as CS4-A output
01: Setting prohibited
10: Specifies pin PF7 as CS4-C output
11: Setting prohibited
Bit 25/17/9/1 Bit 24/16/8/0
CS4SA CS4SB
Rev.2.00 Jun. 28, 2007 Page 659 of 666
Module
I/O port
REJ09B0311-0200