Basic Timing - Renesas H8SX/1650 Hardware Manual

6.7.4

Basic Timing

(1)
2-State Access Space
Figure 6.23 shows the bus timing when the byte control SRAM space is specified as a 2-state
access space.
Data buses used for 16-bit access space is the same as those in basic bus interface. No wait cycles
can be inserted.
Read
Write
Bφ
Address
CSn
AS
LUB
LLB
RD/WR
RD
D15 to D8
D7 to D0
RD/WR
RD
D15 to D8
D7 to D0
BS
Note: n = 0 to 7
Figure 6.23 16-Bit 2-State Access Space Bus Timing
Bus cycle
T T
1 2
Valid
Valid
High level
Valid
Valid
Rev.2.00 Jun. 28, 2007 Page 181 of 666
Section 6 Bus Controller (BSC)
REJ09B0311-0200