Area And External Bus Interface - Renesas H8SX/1650 Hardware Manual

6.5.5

Area and External Bus Interface

(1)
Area 0
Area 0 includes on-chip ROM*. All of area 0 is used as external address space in on-chip ROM
disabled extended mode, and the space excluding on-chip ROM is external address space in on-
chip ROM enabled extended mode.
When area 0 external address space is accessed, the CS0 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or burst ROM interface can be
selected for area 0 by bit BSRM0 in BROMCR and bit BCSEL0 in SRAMCR. Table 6.7 shows
the external interface of area 0.
Note: Applied to the LSI version that incorporates the ROM.
Table 6.7 Area 0 External Interface
Interface
Basic bus interface
Byte control SRAM interface
Burst ROM interface
Setting prohibited
(2)
Area 1
In externally extended mode, all of area 1 is external address space. In on-chip ROM enabled
extended mode, the space excluding on-chip ROM* is external address space.
When area 1 external address space is accessed, the CS1 signal can be output.
Either of the basic bus interface, byte control SRAM, or burst ROM interface can be selected for
area 1 by bit BSRM1 in BROMCR and bit BCSEL1 in SRAMCR. Table 6.8 shows the external
interface of area 1.
Note: Applied to the LSI version that incorporates the ROM.
BSRM0 of BROMCR
0
0
1
1
Section 6 Bus Controller (BSC)
Register Setting
BCSEL0 of SRAMCR
0
1
0
1
Rev.2.00 Jun. 28, 2007 Page 159 of 666
REJ09B0311-0200