Renesas H8SX/1650 Hardware Manual page 210

Section 6 Bus Controller (BSC)
Bφ
Upper
address bus
Lower
address bus
CSn
AS
RD
Data bus
BS
RD/WR
Note: n = 1, 0
Figure 6.27 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle)
Rev.2.00 Jun. 28, 2007 Page 188 of 666
REJ09B0311-0200
Full access
T T
1 2
Burst access
T T
1 1