Sram Mode Control Register (Sramcr) - Renesas H8SX/1650 Hardware Manual

6.2.10

SRAM Mode Control Register (SRAMCR)

SRAMCR specifies the bus interface of each area in the external address space as a basic bus
interface or a byte control SRAM interface.
In areas specified as 8-bit access space by ABWCR, the SRAMCR setting is ignored and the byte
control SRAM interface cannot be specified.
Bit 15
Bit Name BCSEL7
Initial Value 0
R/W R/W
Bit 7

Bit Name
Initial Value 0
R/W R
Bit Bit Name
15 BCSEL7
14 BCSEL6
13 BCSEL5
12 BCSEL4
11 BCSEL3
10 BCSEL2
9 BCSEL1
8 BCSEL0

7 to 0
14 13
BCSEL6 BCSEL5
0 0
R/W R/W
6 5
 
0 0
R R
Initial
Value R/W Description
0 R/W Byte Control SRAM Interface Select
0 R/W Selects the bus interface for the corresponding area.
0 R/W When setting the area n bit to 1, the bus interface
selection bits for the corresponding area in BROMCR and
0 R/W
MPXCR should be cleared to 0.
0 R/W
0: Area n is basic bus interface
0 R/W
1: Area n is byte control SRAM interface
0 R/W
(n = 7 to 0)
0 R/W
All 0 R Reserved
These are read-only bits and cannot be modified.
12 11
BCSEL4 BCSEL3
0 0
R/W R/W
4 3
 
0 0
R R
Rev.2.00 Jun. 28, 2007 Page 141 of 666
Section 6 Bus Controller (BSC)
10 9
BCSEL2 BCSEL1
0 0
R/W R/W
2 1
 
0 0
R R
REJ09B0311-0200
8
BCSEL0
0
R/W
0

0
R