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Section 20 Electrical Characteristics
Bφ
A23 to A0
CS7 to CS0
t
AHD
AH (AS)
RD/WR
RD
Read
D15 to D0
RD/WR
LHWR, LLWR
Write
D15 to D0
WAIT
Figure 20.18 Address/Data Multiplexed Access Timing (Wait Control)
(Address Cycle Program Wait × 1 + Data Cycle Program Wait × 1 +
Rev.2.00 Jun. 28, 2007 Page 638 of 666
REJ09B0311-0200
T
T
ma1
maw
t
AD
t
AHD
t
AHW2
t
MAS2
t
MAD1
t
MAS2
t
MAD1
Data Cycle Pin Wait × 1)
T
T
T
2
ma2
1
t
MAH
t
MAH
t
WDS1
t
t
WTS
WDD
T
T
T
pw
tw
3
t
RDS2
t
t
t
WTH
WTS
WTH
t
RDH2
t
WDH1
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