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Section 6 Bus Controller (BSC)
6.4
Multi-Clock Function and Number of Access Cycles
The internal functions of this LSI operate synchronously with the system clock (Iφ), the peripheral
module clock (Pφ), or the external bus clock (Bφ). Table 6.1 shows the synchronization clock and
their corresponding functions.
Table 6.1
Synchronization Clocks and Their Corresponding Functions
Synchronization Clock
Iφ
Pφ
Bφ
The frequency of each synchronization clock (Iφ, Pφ, and Bφ) is specified by the system clock
control register (SCKCR) independently. For further details, see section 17, Clock Pulse
Generator.
There will be cases when Pφ and Bφ are equal to Iφ and when Pφ and Bφ are different from Iφ
according to the SCKCR specifications. In any case, access cycles for internal peripheral functions
and external space is performed synchronously with Pφ and Bφ, respectively.
For example, in an external address access where the frequency rate of Iφ and Bφ is n : 1, the
operation is performed in synchronization with Bφ. In this case, external 2-state access space is 2n
cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number of
access cycles is counted based on Iφ.
Rev.2.00 Jun. 28, 2007 Page 146 of 666
REJ09B0311-0200
Function Name
MCU operating mode
Interrupt controller
Bus controller
CPU
DTC
Internal memory
Clock pulse generator
Power down control
I/O ports
TPU
PPG
TMR
WDT
SCI
A/D
D/A
External bus interface
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