Buffer Operation - Renesas H8SX/1650 Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.3

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 9.29 shows the register combinations used in buffer operation.
Table 9.29 Register Combinations in Buffer Operation
Channel
0
3
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 9.12.
Buffer register
Rev.2.00 Jun. 28, 2007 Page 354 of 666
REJ09B0311-0200
Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
Compare match signal
Timer general
register
Figure 9.12 Compare Match Buffer Operation
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
Comparator TCNT