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Table 20.6 Bus Timing (2)
Conditions: V
= 3.0 V to 3.6 V, AV
CC
V
= AV
SS
T
= –20°C to +75°C (regular specifications),
a
T
= –40°C to +85°C (wide-range specifications)
a
Item
WR delay time 1
WR delay time 2
WR pulse width 1
WR pulse width 2
Write data delay time
Write data setup time 1
Write data setup time 2
Write data setup time 3
Write data hold time 1
Write data hold time 3
Byte control delay time
Byte control pulse width 1
Byte control pulse width 2
Multiplexed address delay time 1
Multiplexed address hold time
Multiplexed address setup time 1
Multiplexed address setup time 2
Address hold delay time
Address hold pulse width 1
Address hold pulse width 2
WAIT setup time
WAIT hold time
BREQ setup time
BACK delay time
Bus floating time
BREQO delay time
BS delay time
RD/WR delay time
= 3.0 V to 3.6 V, V
CC
= 0 V, Bφ = 8 MHz to 50 MHz,
SS
Symbol
t
WRD1
t
WRD2
t
WSW1
t
WSW2
t
WDD
t
WDS1
t
WDS2
t
WDS3
t
WDH1
t
WDH3
t
UBD
t
UBW1
t
UBW2
t
MAD1
t
MAH
t
MAS1
t
MAS2
t
AHD
t
AHW1
t
AHW2
t
WTS
t
WTH
t
BREQS
t
BACD
t
BZD
t
BRQOD
T
BSD
T
RWD
= 3.0 V to AV
ref
Min.
Max.
15
15
1.0 × t
− 13
cyc
1.5 × t
− 13
cyc
20
0.5 × t
− 13
cyc
1.0 × t
− 13
cyc
1.5 × t
− 13
cyc
0.5 × t
− 8
cyc
1.5 × t
− 8
cyc
15
1.0 × t
2.0 × t
15
1.0 × t
− 15
cyc
0.5 × t
− 15
cyc
1.5 × t
− 15
cyc
15
1.0 × t
− 15
cyc
2.0 × t
− 15
cyc
15
5.0
20
15
30
15
1.0
15
15
Rev.2.00 Jun. 28, 2007 Page 627 of 666
Section 20 Electrical Characteristics
,
CC
Test
Unit
Conditions
ns
Figures 20.8 to
20.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figures 20.13,
20.14
− 15 ns
Figure 20.13
cyc
− 15 ns
Figure 20.14
cyc
ns
Figures 20.17,
20.18
ns
ns
ns
ns
ns
ns
ns
Figures 20.10,
20.18
ns
ns
Figure 20.19
ns
ns
ns
Figure 20.20
ns
Figures 20.8,
20.9, 20.11 to
ns
20.14
REJ09B0311-0200
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