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Output
Specification
Port
Signal Name
P3
1
TIOCB0_OE
PO9_OE
0
TIOCA0_OE
PO8_OE
P6
5
TMO3_OE
2
TMO2_OE
SCK4_OE
0
TxD4_OE
PA
7
Bφ_OE
AH_OE
6
BS-B_OE
AS_OE
RD_OE
5
LUB_OE
4
LHWR_OE
LLB_OE
3
LLWR_OE
BACK_OE
1
(RD/WR)_OE
BS-A_OE
0
BREQO_OE
Output
Signal
Signal Selection
Name
Register Settings
TIOCB0
PO9
TIOCA0
PO8
TMO3
TMO2
SCK4
TxD4
Bφ
AH
BS
PFCR2.BSS = 1
AS
RD
LUB
LHWR
LLB
LLWR
BACK
RD/WR
BS
PFCR2.BSS = 0
BREQO
Peripheral Module Settings
TPU.TIORH0.IOB3 = 0,
TPU.TIORH0.IOB[1,0] = 01/10/11
NDERH.NDER9 = 1
TPU.TIORH0.IOA3 = 0,
TPU.TIORH0.IOA[1,0] = 01/10/11
NDERH.NDER8 = 1
TCSR.OS[3,2] = 01/10/11 or TCSR.OS[1,0] = 01/10/11
TCSR.OS[3,2] = 01/10/11 or TCSR.OS[1,0] = 01/10/11
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE [1, 0] = 01 or
while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1 while
SMR.C/A = 0, SCR.CKE [1, 0] = 01 or
while SMR.C/A = 1, SCR.CKE 1 = 0
SCR.TE = 1
PADDR.PA7DDR = 1, SCKCR.POSEL1 = 0
MPXCR.MPXEn (n = 7 to 3) = 1
PFCR2.BSE = 1
PFCR2.ASOE = 1
PFCR6.LHWROE = 1 or SRAMCR.BCSELn = 1
PFCR6.LHWROE = 1
SRAMCR.BCSELn = 1
SRAMCR.BCSELn = 0
BCR1.BRLE = 1
PFCR2.REWRE = 1 or SRAMCR.BCSELn = 1
PFCR2.BSE = 1
BCR1.BRLE = 1, BCR1.BREQOE = 1
Rev.2.00 Jun. 28, 2007 Page 289 of 666
Section 8 I/O Ports
REJ09B0311-0200
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