Data Bus; I/O Pins Used For Burst Rom Interface - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.8.2

Data Bus

The bus width of the burst ROM space can be specified as 8-bit or16-bit burst ROM interface
space according to the ABWHn and ABWLn bits (n = 0, 1) in ABWCR.
For the 8-bit bus width, data bus (D7 to D0) is valid. For the 16-bit bus width, data bus (D15 to
D0) is valid.
Access size and data alignment are the same as the basic bus interface. For details, see section
6.5.6, Endian and Data Alignment.
6.8.3

I/O Pins Used for Burst ROM Interface

Table 6.17 shows the pins used for the burst ROM interface.
Table 6.17 I/O Pins Used for Burst ROM Interface
Name
Bus cycle start
Address strobe
Read strobe
Read/write
Low-high write
Low-low write
Chip select 0. 1
Wait
Rev.2.00 Jun. 28, 2007 Page 186 of 666
REJ09B0311-0200
Symbol I/O
BS
Output
AS
Output
RD
Output
RD/WR Output
LHWR
Output
LLWR
Output
CS0, CS1
Output
WAIT
Input
Function
Signal indicating that the bus cycle has started.
Strobe signal indicating that an address output on the
address bus is valid during access
Strobe signal indicating the read access
Signal indicating the data bus input or output direction
Strobe signal indicating that the upper byte (D15 to
D8) is valid during write access
Strobe signal indicating that the lower byte (D7 to D0)
is valid during write access
Strobe signal indicating that the area is selected
Wait request signal used when an external address
space is accessed