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Section 6 Bus Controller (BSC)
(2)
3-State Access Space
Figure 6.24 shows the bus timing when the byte control SRAM space is specified as a 3-state
access space.
Data buses used for 16-bit access space is the same as those in the basic bus interface. Wait cycles
can be inserted.
Bφ
Address
CSn
AS
LUB
LLB
RD/WR
RD
Read
D15 to D8
D7 to D0
RD/WR
RD
Write
D15 to D8
D7 to D0
BS
Note: n = 0 to 7
Rev.2.00 Jun. 28, 2007 Page 182 of 666
REJ09B0311-0200
T
1
Figure 6.24 16-Bit 3-State Access Space Bus Timing
Bus cycle
T
2
Valid
Valid
High level
Valid
Valid
T
3
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