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Section 6 Bus Controller (BSC)
If the frequencies of Iφ, Pφ and Bφ are different, the start of bus cycle may not synchronize with
Pφ or Bφ according to the bus cycle initiation timing. In this case, clock synchronization cycle
(Tsy) is inserted at the beginning of each bus cycle.
For example, if an external address access occurs when the frequency rate of Iφ and Bφ is
n : 1, 0 to n-1 cycles of Tsy may be inserted. If an internal peripheral module access occurs when
the frequency rate of Iφ and Pφ is m : 1, 0 to m-1 cycles of Tsy may be inserted.
Figure 6.5 shows the external 2-state access timing when the frequency rate of Iφ and Bφ is 4 : 1.
Figure 6.6 shows the external 3-state access timing when the frequency rate of Iφ and Bφ is 2 : 1.
Rev.2.00 Jun. 28, 2007 Page 147 of 666
REJ09B0311-0200
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