Idle Control Register (Idlcr) - Renesas H8SX/1650 Hardware Manual

Bφ
Address
CSn
AS
BS
RD/WR
RD
Read
Data bus
LHWR, LLWR
Write
Data bus
Figure 6.3 CS and Address Assertion Period Extension
(Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0)
6.2.6

Idle Control Register (IDLCR)

IDLCR specifies the idle cycle insertion conditions and the number of idle cycles.
Bit 15

Bit Name
Initial Value 1
R/W R/W
Bit 7
Bit Name IDLSEL7
Initial Value 0
R/W R/W
T
h
14 13
IDLS2 IDLS1
1 1
R/W R/W
6 5
IDLSEL6 IDLSEL5
0 0
R/W R/W
Bus cycle
T T
1 2
Read data
Write data
12 11
IDLS0 IDLCB1
1 1
R/W R/W
4 3
IDLSEL4 IDLSEL3
0 0
R/W R/W
Rev.2.00 Jun. 28, 2007 Page 135 of 666
Section 6 Bus Controller (BSC)
T T
3 t
10 9
IDLCB0 IDLCA1
1 1
R/W R/W
2 1
IDLSEL2 IDLSEL1
0 0
R/W R/W
REJ09B0311-0200
8
IDLCA0
1
R/W
0
IDLSEL0
0
R/W