Renesas H8SX/1650 Hardware Manual page 418

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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Section 10 Programmable Pulse Generator (PPG)
• NDRH
If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the
same address and can be accessed at one time, as shown below.
Bit
Bit Name
7
NDR15
6
NDR14
5
NDR13
4
NDR12
3
NDR11
2
NDR10
1
NDR9
0
NDR8
If pulse output groups 2 and 3 have different output triggers, the upper four bits and lower four
bits are mapped to different addresses as shown below.
Bit
Bit Name
7
NDR15
6
NDR14
5
NDR13
4
NDR12
3 to 0
Bit
Bit Name
7 to 4
3
NDR11
2
NDR10
1
NDR9
0
NDR8
Rev.2.00 Jun. 28, 2007 Page 396 of 666
REJ09B0311-0200
Initial
Value
R/W
Description
0
R/W
Next Data Register 15 to 8
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger specified
0
R/W
with PCR.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
R/W
Description
0
R/W
Next Data Register 15 to 12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger specified
0
R/W
with PCR.
0
R/W
All 1
Reserved
These bits are always read as 1 and cannot be modified.
Initial
Value
R/W
Description
All 1
Reserved
These bits are always read as 1 and cannot be modified.
0
R/W
Next Data Register 11 to 8
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger specified
0
R/W
with PCR.
0
R/W

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