Basic Timing - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.6.3

Basic Timing

This section describes the basic timing when the data is specified as big endian.
(1)
16-Bit 2-State Access Space
Figures 6.14 to 6.16 show the bus timing of 16-bit 2-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles
can be inserted.
Read
Write
Rev.2.00 Jun. 28, 2007 Page 168 of 666
REJ09B0311-0200
Bφ
Address
CSn
AS
RD
D15 to D8
D7 to D0
LHWR
LLWR
D15 to D8
D7 to D0
BS
RD/WR
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.14 16-Bit 2-State Access Space Bus Timing
(Byte Access for Even Address)
Bus cycle
T T
1 2
Valid
Invalid
High level
Valid
High-Z