Standby Control Register (Sbycr) - Renesas H8SX/1650 Hardware Manual

Section 18 Power-Down States
18.2.1

Standby Control Register (SBYCR)

SBYCR controls software standby mode.
Bit 15
Bit Name SSBY
Initial Value 0
R/W R/W
Bit 7
Bit Name SLPIE
Initial Value 0
R/W R/W
Bit Bit Name
15 SSBY
14 OPE
Rev.2.00 Jun. 28, 2007 Page 566 of 666
REJ09B0311-0200
14 13

OPE
1 0
R/W R/W
6 5
 
0 0
R/W R/W
Initial
Value R/W Description
0 R/W Software Standby
Specifies the transition mode after executing the SLEEP
instruction
0: Shifts to sleep mode after the SLEEP instruction is
1: Shifts to software standby mode after the SLEEP
This bit does not change when clearing the software
standby mode by using external interrupts and shifting to
normal operation. For clearing, write 0 to this bit. When
the WDT is used as the watchdog timer, the setting of this
bit is disabled. In this case, a transition is always made to
sleep mode or all-module-clock-stop mode after the
SLEEP instruction is executed.
This bit should be cleared to 0 when setting the SLPIE bit
to 1.
1 R/W Output Port Enable
Specifies whether the output of the address bus and bus
control signals (CS0 to CS7, AS, RD, HWR, and LWR) is
retained or set to the high-impedance state in software
standby mode.
0: In software standby mode, address bus and bus
1: In software standby mode, address bus and bus
12 11
STS4 STS3
0 1
R/W R/W
4 3
 
0 0
R/W R/W
executed
instruction is executed
control signals are high-impedance
control signals retain output state
10 9
STS2 STS1
1 1
R/W R/W
2 1
 
0 0
R/W R/W
8
STS0
1
R/W
0

0
R/W