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Section 6 Bus Controller (BSC)
(3)
Read after Write
If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7).
Figure 6.36 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted,
and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM
device. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bφ
Address bus
CS (area A)
CS (area B)
RD
LLWR
Data bus
(a) No idle cycle inserted
Figure 6.36 Example of Idle Cycle Operation (Read after Write)
Rev.2.00 Jun. 28, 2007 Page 202 of 666
REJ09B0311-0200
Bus cycle B
Bus cycle A
T
T
T
T
T
1
2
3
1
Output floating time is large
(IDLS2 = 0)
Bus cycle A
T
2
1
Data conflict
(IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0)
Bus cycle B
T
T
T
T
T
2
3
i
1
(b) Idle cycle inserted
2
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