Renesas H8SX/1650 Hardware Manual page 67

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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Instruction
Size
BCLR/cc
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
BXOR
B
Function
if cc, 0 → (<bit-No.> of <EAd>)
If the specified condition is satisfied, this instruction clears a specified bit
in a memory location to 0. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.
∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in the contents of a general register or a memory
location. The bit number is specified by 3-bit immediate data or the lower
three bits of a general register.
∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in the contents of a general register or a memory
location and sets or clears the Z flag accordingly. The bit number is
specified by 3-bit immediate data or the lower three bits of a general
register.
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
C ∧ [∼ (<bit-No.> of <EAd>)] → C
Logically ANDs the carry flag with the inverse of a specified bit in the
contents of a general register or a memory location and stores the result
in the carry flag.
The bit number is specified by 3-bit immediate data.
C ∨ (<bit-No.> of <EAd>) → C
Logically ORs the carry flag with a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
C ∨ [∼ (<bit-No.> of <EAd>)] → C
Logically ORs the carry flag with the inverse of a specified bit in the
contents of a general register or a memory location and stores the result
in the carry flag.
The bit number is specified by 3-bit immediate data.
C ⊕ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with a specified bit in the contents
of a general register or a memory location and stores the result in the
carry flag.
The bit number is specified by 3-bit immediate data.
Rev.2.00 Jun. 28, 2007 Page 45 of 666
REJ09B0311-0200
Section 2 CPU

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