Address Error; Address Error Source - Renesas H8SX/1650 Hardware Manual

Section 4 Exception Handling
4.5

Address Error

4.5.1

Address Error Source

Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address
error.
Table 4.5 Bus Cycle and Address Error
Bus Cycle
Type Bus Master
Instruction CPU
fetch
Stack CPU
operation
Data CPU
read/write
Data DTC
read/write
Notes: 1. For on-chip peripheral module space, see section 6, Bus Controller (BSC).
2. For the access-prohibited area, see figure 3.1, Address Map (Advanced Mode) in
section 3.4, Address Map.
Rev.2.00 Jun. 28, 2007 Page 76 of 666
REJ09B0311-0200
Description
Fetches instructions from even addresses
Fetches instructions from odd addresses
Fetches instructions from areas other than on-chip
peripheral module space*
Fetches instructions from on-chip peripheral module
1
space*
Fetches instructions from external memory space in
single-chip mode
Fetches instructions from access prohibited area.*
Accesses stack when the stack pointer value is even
address
Accesses stack when the stack pointer value is odd Occurs
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-chip
mode
Accesses to access prohibited area*
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-chip
mode
Accesses to access prohibited area*
1
2
2
Address Error
No (normal)
Occurs
No (normal)
Occurs
Occurs
2
Occurs
No (normal)
No (normal)
No (normal)
Occurs
Occurs
No (normal)
No (normal)
Occurs
Occurs